PIC18F452-I/ML【PDF 62/134 页】IC MCU FLASH 16KX16 A/D 44QFN

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Micrel, Inc.

KSZ8864RMN

April 2012

M9999-043012-1.5

The default of the device is clock mode because the P1LED1 is pulled up internally, the clock mode means the clock

source comes from 25MHz crystal/oscillator on pins X1/X2, and the 50MHz clock will be output from the SMxRXC pin in

RMII interface to be used, the 50MHz can be disabled by the register 87 bit 3 and bit 2 for SM4RXC and SM3RXC if the

reference clock is not used. For the detail RMII connection samples, please refer to the application note in the design kit.

Advanced Functionality

QoS Priority Support

The KSZ8864RMN provides Quality of Service (QoS) for applications such as VoIP and video conferencing. The

KSZ8864RMN offer 1/2/4 priority queues option per port by setting the port registers xxx control 9 bit1 and the port

registers xxx control 0 bit0, the 1/2/4 queues split as follows:

[Port registers xxx control 9 bit1, control 0 bit0]=00 single output queue as default.

[Port registers xxx control 9 bit1, control 0 bit0]=01 egress port can be split into two priority transmit queues.

[Port registers xxx control 9 bit1, control 0 bit0]=10 egress port can be split into four priority transmit queues.

The four priority transmit queues is a new feature in the KSZ8864RMN. The queue 3 is the highest priority queue and

Queue 0 is the lowest priority queue. The port registers xxx control 9 bit1 and the port registers xxx control 0 bit0 are used

to enable split transmit queues for ports 1and 2, respectively. If a port's transmit queue is not split, high priority and low

priority packets have equal priority in the transmit queue.

There is an additional option to either always deliver high priority packets first or use programmable weighted fair queuing

for the four priority queues scale by the port registers control 10, 11, 12 and 13 (default value are 8, 4, 2, 1 by their

bit[6:0].

Register 130 bit[7:6] Prio_2Q[1:0] is used when the 2 Queue configuration is selected, these bits are used to map the 2-bit

result of IEEE 802.1p from the registers 128, 129 or TOS/DiffServ mapping from registers 144-159 (for four Queues) into

two queues mode with priority high or low.

Please see the descriptions of the register 130 bits [7:6] for details.

Port-Based Priority

With port-based priority, each ingress port is individually classified as a priority 0-3 receiving port. All packets received at

the priority 3 receiving port are marked as high priority and are sent to the high-priority transmit queue if the corresponding

transmit queue is split. The Port Registers Control 0 Bits [4:3] is used to enable port-based priority for ports 1and 2,

respectively.

802.1p-Based Priority

For 802.1p-based priority, the KSZ8864RMN examines the ingress (incoming) packets to determine whether they are

tagged. If tagged, the 3-bit priority field in the VLAN tag is retrieved and compared against the “priority mapping” value, as

specified by the registers 128 and 129, both register 128/129 can map 3-bit priority field of 0-7 value to 2-bit result of 0-3

priority levels. The “priority mapping” value is programmable.

Figure 6 illustrates how the 802.1p priority field is embedded in the 802.1Q VLAN tag.

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